ASIC RTL Design Technical Lead Job Listing at AMD in San Jose, CA (Job ID 72146-en-us)

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

THE ROLE:

A senior technical contributor that drives end-to-end delivery of SerDes solution directly contributing to and coordinating implementation and optimization across multiple teams. The position will involve interfacing with software and hardware engineering teams and AMD partners to plan, develop and optimize use cases. This is an exciting opportunity to work on the cutting edge of SerDes Technology.

THE PERSON:

You are a subject matter expert and strong technical contributor with SerDes/PHY experience. You excel as part of a team where communication and team skills are highly valued.

KEY RESPONSIBILITIES:

As an ASIC Design Engineer, your responsibilities span various aspects of SOC design:

• Write microarchitecture and/or design specifications 
• Design, implement, and debug complex logic designs 
• Integrate complex IPs into the SOC
• Work with other specialists that are members of the SOC Design - Verification, Emulation, STA, and Physical Design teams  
• Support all front end integration activities (Lint, CDC, Synthesis, and ECO) 
• Implement design automation via Python or other languages 
• Collaborate with software and systems teams to ensure a high quality system

PREFERRED EXPERIENCE:

• Hands on experience in all aspects of the chip development process with proficiency in front end tools and methodologies
• Writing specifications and converting them to design
• Experience or knowledge of system architecture, CPU & IP Integration, and power and clock management designs is highly desirable
• Experience in front-end implementation tasks such as synthesis, timing, area/power analysis, linting, and logic equivalence checks.
• Experience in low-power design techniques such as clock- and power-gating is a plus
• Ability to communicate effectively across all internal groups
• Familiarity with scripting languages like Perl or Python or Tcl is a plus
• Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB) is a plus
• Familiarity with security concepts is a plus
• Familiarity with software and operating concepts is a plus
• Excellent communication and collaboration skills

ACADEMIC CREDENTIALS:

• Bachelor's or Master's degree in related discipline preferred

LOCATION: San Jose, CA, or anywhere in the US

#LI-TB2

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.