Physical Design Lead – Full Chip & Chiplet SoC Job Listing at AMD in Hyderabad, Telangana (Job ID 86545-en-us)

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

PMTS SILICON DESIGN ENGINEER

THE ROLE:

We are seeking a seasoned Physical Design Lead with expertise or significant interest in handling complete Physical Design for a complex Chiplet. You have had significant success driving Full Chip Floorplan based on architecture, Defining Timing targets across PVT's, drive for Full Chip PnR and Tile PnR closure and monitor Signoff functions like Physical Verification, IREM etc., You are meticulous about Power, Performance and Area while keeping schedule in tact. This role also stretch you as a overall PD lead to work with IP teams, Architecture, Package and CAD/Methodology teams. 

THE PERSON:

You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc.  You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.

KEY RESPONSIBILITIES:

• Own the Physical Design for one complete Chiplet on advanced technology nodes preferably TSMC 2nm or 3nm.
• Work with all external stakeholders like Architects, IP teams, CAD/Methodology teams and all internal PD stakeholders like FCFP, FCT, TilePnR, PV from technical standpoint
• Drive for best PPA attainments, optimize latency on datapaths,  work with package teams on power delivery and other interdependencies
• Signoff the Chiplet for Tapeout from Physical Design aspect

 PREFERRED EXPERIENCE:

• 15+ years of experience in Physical Design handling full chip activities and signoff
• Excellent communication, management, and presentation skills.
• Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies

 ACADEMIC CREDENTIALS:

• Bachelor's or Master's degree in related discipline preferred

#LI-PK2

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD's “Responsible AI Policy” is available here.

This posting is for an existing vacancy.