Senior Silicon Design Engineer Job Listing at AMD in San Jose, CA (Job ID 73314-en-us)

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

THE ROLE

We are seeking a Senior Member of Technical Staff (SMTS) SoC Architect to join our SoC Architecture team. In this role, you will define and drive architecture for critical SoC functions across roadmap and custom devices. You will focus on chip pervasive components, while ensuring seamless integration with processor subsystems, interconnect, AI accelerators, and memory systems.

THE PERSON

You are passionate about complex SoC architecture and thrive in cross-functional environments. You have deep technical expertise, strong analytical skills, and the ability to balance performance, power, and area trade-offs. You communicate effectively across teams and are comfortable influencing architecture decisions for next-generation silicon.

KEY RESPONSIBILITIES

• Define and develop SoC architecture for CPF components, including Analog IPs, clocking/reset, and silicon monitors.
• Collaborate with processor, interconnect, AI, and memory subsystem architects to ensure cohesive system-level design.
• Specify architecture requirements, conduct early-stage analysis, and create detailed specifications.
• Drive PPA optimization and ensure scalability across roadmap and custom devices.
• Partner with design, verification, and physical implementation teams to ensure functional correctness and timing closure.
• Analyze trade-offs for performance, power, reliability, and manufacturability.
• Influence strategies for security, safety, and reliability across CPF domains.
• Strong communication and leadership skills to influence cross-functional teams.

PREFERRED EXPERIENCE

• Strong background in SoC architecture, including processor subsystems, interconnect, memory systems, and AI accelerators.
• Expertise in Analog IPs (IOs, PLLs, eFuses, monitors), clocking/reset architecture, and silicon lifecycle management.
• Familiarity with SoC on-chip protocols (e.g., AXI) and system-level QoS.
• Experience with low-power design techniques, boot/reset flows, and power management.
• Knowledge of design methodologies, advanced process technologies, and associated challenges.
• Proficiency in modeling and automation using Python, SystemC, or similar languages.

ACADEMIC & EXPERIENCE REQUIREMENTS

• BS or MS or PhD in Electrical/Computer Engineering or related field.
• Proven track record in delivering architecture for high-performance, low-power SoCs.

LOCATION: San Jose, California

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.