Silicon Design Engineer Job Listing at AMD in Shanghai, Shanghai (Job ID 81062-en-us)

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

THE ROLE: 

AMD is seeking a motivated SMTS/MTS-level DFX RTL Designer to join the Central DFX (CDFX) organization. In this role, you will design, integrate, and deliver Design-for-Test (DFT/DFX) RTL solutions and supporting flows for advanced SoCs across AI data center, embedded, gaming, and PC markets. You will work closely with design, verification, physical design, product engineering, and ATE/test teams to ensure AMD silicon is testable, debuggable, and manufacturable at scale.

THE PERSON:

You are a hands-on RTL designer with strong DFX fundamentals and a track record of delivering production-quality test logic on complex SoCs. You enjoy collaborating across teams, have solid debugging skills, and can drive tasks from definition through implementation, verification, and silicon bring-up. You communicate clearly, document your work well, and thrive in a fast-paced environment.

KEY RESPONSIBLITIES:

DFX RTL Design & Integration

• Develop and maintain DFX RTL, including scan architecture support, test control logic, and DFX infrastructure integrated into large-scale SoC/CPU/GPU designs.
• Implement key DFT/DFX features such as scan insertion readiness, MBIST/LBIST support logic, boundary scan/JTAG, and other test/debug hooks as required by project methodology.
• Drive DFX deliverables through the full lifecycle: requirements/spec → RTL implementation → verification signoff → integration → bring-up support.

DFT/DFX Flow Execution & Methodology

• Execute and support DFX implementation steps such as scan insertion, ATPG enablement, BIST integration, and related checks with standard industry tools (e.g., Siemens Tessent, Synopsys DFT/ATPG toolchains, as applicable).
• Partner with internal methodology teams to improve DFX RTL quality, automation, lint/CDC/RDC readiness, low-power test considerations, and hierarchical DFT approaches.
• Create and maintain clear documentation (micro-architecture specs, integration guides, and bring-up notes).

Debug, Bring-up, and Cross-Functional Collaboration

• Collaborate with SOC/design, DV, PD/STA, timing closure, firmware, and product/test engineering to resolve DFX-related issues efficiently.
• Support post-silicon debug and yield/coverage improvements by analyzing failures and driving fixes into RTL/flows.

PREFERRED EXPERIENCE:

• Strong experience in RTL design (SystemVerilog/Verilog) and integration on complex SoCs.
• Solid understanding of DFX/DFT concepts: scan chains, ATPG, fault models, MBIST/LBIST, JTAG/boundary scan, test compression (nice to have), and low-power test considerations.
• Experience using DFT/DFX EDA tools (e.g., Tessent, Synopsys DFT/ATPG) and interpreting coverage/reports/debug artifacts.
• Ability to debug complex issues spanning RTL, netlist, constraints, and tool flows.
• Strong collaboration and communication skills across globally distributed teams.
• Self-driven ownership mindset; able to manage multiple deliverables and priorities.
• Strong English communication skills, including effective speaking and listening in technical discussions across cross-functional and global teams.
• Leveraging AI-assisted tools to improve RTL design productivity, including code generation, refactoring, documentation, and debug support, while maintaining strong engineering judgment and adherence to coding/quality guidelines.

ACADEMIC CREDENTIALS:

• B.S. (7 years+) or M.S. (5 years+) degree in Electrical Engineering (EE), Computer Science (CS), Computer Engineering, or a related field.

LOCATION: Shanghai

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD's “Responsible AI Policy” is available here.

This posting is for an existing vacancy.