Soc physical verification Engineer Job Listing at AMD in Hyderabad, TS (Job ID 76010-en-us)

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

SENIOR SILICON DESIGN ENGINEER 

 

THE ROLE:  The focus of this role is to work on custom layout, full chip integration and physical verification activities of FPGA/SOC designs. This role requires strong analytical and debug skills for solving full chip DRC/LVS/Antenna issues. You would be required to write scripts in TCL/Python to automate the integration flows. You would also be required to closely interact with different teams including PD, CAD, EMIR and PKG teams for successful integration of IPs into full chip.     THE PERSON:   Master's/Bachelor's Degree in Electrical/Electronic engineering with 6+ years of experience in Macro/SOC level full chip physical verification is required. Exposure to PDK updates, bump/ubump layout is desired. Strong scripting skills in TCL/Python is must.   Successful candidate would be responsible for full chip integration and physical verification of 7nm and lower node FPGA/SOC designs. You will be actively working with CAD, PD and EMIR teams for seamless integration of IPs into full chip. This job requires excellent teamwork, great communication and strong problem-solving skill.   KEY RESPONSIBILITIES:  

• Full chip integration and physical verification of FPGA/SOC designs
• Debug the full chip LVS/DRC/Antenna issues with multi point approach
• Work closely with PD, CAD, SiTech, EMIR, PKG and EDA vendors for seamless integration of IPs into full chip for ontime tapeout.
• Write automation scripts in TCL/Python to improve integration flows efficiency.
• Custom layout of 7nm and lower nodes integration blocks.
• Handle hierarchical designs and large DRC/Antenna counts
• Exposure to OAS/GDSII viewing tools such as calibredrv is desirable.

  PREFERRED EXPERIENCE:  

• Should be well versed with FinFet technology DRC debugging and fixes.
• Strong debug capabilities with parasitic extraction, LVS/DRC/Antenna and other Physical verification checks.
• Knowledge of scripting languages like SKILL, PERL, TCL etc. is must.
• Strong problem solving skills and excellent communication skills.
• Sound knowledge of hierarchical layout handling including macros and full chip.
• Knowledge in PDK (DRC/LVS rule files) is preferred.
• Experience in bump & ubump layouts and 3D integration of AoA or SSIT designs will be desirable.

  ACADEMIC CREDENTIALS:  

• Bachelors or Masters degree in computer engineering/Electrical Engineering 

 

#LI -SR4 

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

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