Sr. Manager Design Verification Engineering Job Listing at AMD in Santa Clara, CA (Job ID 80772-en-us)

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

About the department

Central DFX (CDFX) is a centralized ASIC design group within AMD's Technology and Engineering organization.  CDFX has a global footprint with design teams located in several AMD offices in North America and Asia.  Our mandate is to optimize and standardize design methodology, design and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for complex state-of-the-art APU computing, game console and GPU graphics products.  It is also responsible for DFX design methodology and CAD automation tools development to support the global DFX engineering teams across AMD.

The Role

As an Engineering Manager for the CDFX Design Verification team, you will lead a team of skilled verification engineers in developing and executing verification strategies for AMD's DFT IP. You will be responsible for team leadership, project delivery, technical guidance, and cross-functional coordination to ensure first-pass silicon success for next-generation AMD CPUs, GPUs, and APUs.

Key Responsibilities

• Lead and manage a team of design verification engineers, providing technical direction, mentorship, and performance feedback.
• Define and drive verification strategy for DFT IP, ensuring alignment with architectural goals, schedule, and quality targets.
• Oversee test plan creation, review, and execution for block- and system-level verification.
• Ensure functional and code coverage closure, and track verification quality metrics for all deliverables.
• Collaborate with design, architecture, and performance engineering teams to resolve complex technical issues and optimize verification approaches.
• Prioritize and allocate resources across multiple verification tasks and projects, balancing execution speed with quality.
• Champion verification methodology improvements, automation initiatives, and best practices across the team.
• Support post-silicon debug efforts, helping to recreate and root-cause lab or customer-found issues.
• Represent the verification team in project reviews, planning meetings, and executive updates.

Preferred Skills & Experience

• Proven track record of leading ASIC or SoC design verification teams through successful product tape-outs.
• Strong expertise in SystemVerilog, UVM, and coverage-driven verification methodologies.
• Deep understanding of computer architecture, digital logic design
• Hands-on experience with EDA tools (Synopsys VCS, Cadence Xcelium, Mentor Questa).
• Debugging and problem-solving skills for complex, multi-clock domain designs.
• Strong people management and communication skills to lead geographically distributed teams.

ACADEMIC CREDENTIALS:

• Bachelor's or Master's degree in electrical engineering, Computer Engineering, or a related field preferred

LOCATION: Santa Clara, ca

This role is not eligible for visa sponsorship.

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD's “Responsible AI Policy” is available here.

This posting is for an existing vacancy.