Sr. Silicon Design Engineer (FEINT) Job Listing at AMD in Bayan Lepas, Penang (Job ID 66294-en-us)

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

THE ROLE: 

As part of the AECG ASIC/Custom silicon team, we are looking for an adaptive, self-motivative Front-End SOC silicon design engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market.

THE PERSON: 

As a Front-End SOC Engineer, you will work with chip architects to conceive design, help with architecture/product definition through early involvement in the product life-cycle.

KEY RESPONSIBILITIES: 

• Plan/deliver IP level RTL, and implement front-end RTL integration   
• Experience in ASIC/SoC front-end (preferably RTL Verilog and VHDL based) design and methodologies.  
• Knowledge in frontend design experience on IPs involve processor based sub-system, Serial Standard interfaces, Memory controllers  
• Exposure to Low-power design, System Security considered as added advantage  
• Hands on front-end design of complex multi clock domain blocks  
• Fluency in design & verification languages such as VHDL, Verilog, and System Verilog. 
• Good in scripting, ie. TCL, shell script, Perl, Python 
• Experience in Spyglass for lint and CDC checks.  
• Experience in synthesis and LEC flow.  
• Experience in identifying and implementing complex ECO in netlist.  
• Defining and debugging SDC timing constraints.  
• Optimize the design to meet power, performance, area and timing requirements  
• Write easily readable and synthesizable Verilog RTL  
• Create well written block level design documentation  
• Participate in post silicon functional and performance debug and tuning  
• Self-driven and capable for independent work and independent decision making.   

PREFERRED EXPERIENCE: 

• Hands on experience in RTL coding required, including IP RTL integration 
• Strong understanding of SOC like clocking, reset, boot and power management flows, low power design techniques, security  
• Expertise with quality checks like CDC, Lint, VCLP, LEC  
• Strong technical engineer who communicates well with great collaboration skills
• Experience in RISC-V, NOC, DMA, bus interfaces ie. APB, AHB, AXI, OBI
• Experience in IPs like PCIe & DDR4/5 will be an advantage 
• Experience in packet processing, wireless protocols etc.  
• Experience in wireless, base station protocols will be helpful (CPRI, JESD, Uplink/Downlink) would be helpful.   

ACADEMIC CREDENTIALS: 

• Bachelors or Masters degree in computer engineering/Electrical Engineering.

LOCATION:

Penang, Malaysia

#LI-JK1

#LI-Hybrid 

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.